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Ȩ Ȩ > ¿¬±¸¹®Çå > ±¹³» ³í¹®Áö > Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)

Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)

Current Result Document :

ÇѱÛÁ¦¸ñ(Korean Title) 224-ºñÆ® ¼Ò¼öü Ÿ¿ø°î¼±À» Áö¿øÇÏ´Â °ø°³Å° ¾ÏÈ£ ÇÁ·Î¼¼¼­ÀÇ Àú¸éÀû ±¸Çö
¿µ¹®Á¦¸ñ(English Title) A small-area implementation of public-key cryptographic processor for 224-bit elliptic curves over prime field
ÀúÀÚ(Author) ¹Úº´°ü   ½Å°æ¿í   Byung-Gwan Park   Kyung-Wook Shin  
¿ø¹®¼ö·Ïó(Citation) VOL 21 NO. 06 PP. 1083 ~ 1091 (2017. 06)
Çѱ۳»¿ë
(Korean Abstract)
NIST Ç¥ÁØ¿¡ Á¤ÀÇµÈ ¼Ò¼öü(prime field) GF(p)»óÀÇ 224-ºñÆ® Ÿ¿ø°î¼±À» Áö¿øÇϴ Ÿ¿ø°î¼± ¾ÏÈ£ ÇÁ·Î¼¼¼­¸¦ ¼³°èÇÏ¿´´Ù. Ÿ¿ø°î¼± ¾ÏÈ£ÀÇ ÇÙ½É ¿¬»êÀÎ ½ºÄ®¶ó Á¡ °ö¼ÀÀ» ¼öÁ¤Çü Montgomery ladder ¾Ë°í¸®µëÀ» ÀÌ¿ëÇÏ¿© ±¸ÇöÇÏ¿´´Ù. Á¡ µ¡¼À°ú Á¡ µÎ¹è ¿¬»êÀº Åõ¿µ(projective) ÁÂÇ¥°è¸¦ ÀÌ¿ëÇÏ¿© ¿¬»ê·®ÀÌ ¸¹Àº ³ª´°¼À ¿¬»êÀ» Á¦°ÅÇÏ¿´À¸¸ç, ¼Ò¼öü »óÀÇ µ¡¼À, »¬¼À, °ö¼À, Á¦°ö ¿¬»ê¸¸À¸·Î ±¸ÇöÇÏ¿´´Ù. ½ºÄ®¶ó Á¡ °ö¼ÀÀÇ ÃÖÁ¾ °á°ú°ªÀº ´Ù½Ã ¾ÆÇÉ(affine) ÁÂÇ¥°è·Î º¯È¯µÇ¾î Ãâ·ÂÇϸç, À̶§ »ç¿ëµÇ´Â ¿ª¿ø ¿¬»êÀº Fermat¡¯s little theoremÀ» ÀÌ¿ëÇÏ¿© ±¸ÇöÇÏ¿´´Ù. ¼³°èµÈ ECC ÇÁ·Î¼¼¼­¸¦ Virtex5 FPGA·Î ±¸ÇöÇÏ¿© Á¤»ó µ¿ÀÛÇÔÀ» È®ÀÎÇÏ¿´´Ù. 0.18§­ °øÁ¤ÀÇ CMOS ¼¿ ¶óÀ̺귯¸®·Î ÇÕ¼ºÇÑ °á°ú 10 MHzÀÇ µ¿ÀÛ ÁÖÆļö¿¡¼­ 2.7-Kbit RAM°ú 27,739 GE·Î ±¸ÇöµÇ¾ú°í, ÃÖ´ë 71 MHzÀÇ µ¿ÀÛ ÁÖÆļö¸¦ °®´Â´Ù. ½ºÄ®¶ó Á¡ °ö¼À¿¡ 1,326,985 Ŭ·Ï »çÀÌŬÀÌ ¼Ò¿äµÇ¸ç, ÃÖ´ë µ¿ÀÛ ÁÖÆļö¿¡¼­ 18.7 msecÀÇ ½Ã°£ÀÌ ¼Ò¿äµÈ´Ù.
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(English Abstract)
This paper describes a design of cryptographic processor supporting 224-bit elliptic curves over prime field defined by NIST. Scalar point multiplication that is a core arithmetic function in elliptic curve cryptography(ECC) was implemented by adopting the modified Montgomery ladder algorithm. In order to eliminate division operations that have high computational complexity, projective coordinate was used to implement point addition and point doubling operations, which uses addition, subtraction, multiplication and squaring operations over GF(p). The final result of the scalar point multiplication is converted to affine coordinate and the inverse operation is implemented using Fermat¡¯s little theorem. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 2.7-Kbit RAM and 27,739 gate equivalents (GEs), and the estimated maximum clock frequency is 71 MHz. One scalar point multiplication takes 1,326,985 clock cycles resulting in the computation time of 18.7 msec at the maximum clock frequency.
Å°¿öµå(Keyword) Ÿ¿ø°î¼± ¾ÏÈ£   Åõ¿µ ÁÂÇ¥°è   Jacobian ÁÂÇ¥°è   Æ丣¸¶ÀÇ ¼ÒÁ¤¸®   ECDH Å° ±³È¯ ÇÁ·ÎÅäÄÝ   ECC   projective coordinate   Jacobian¡¯s coordinate   Fermat¡¯s little theorem   ECDH key exchange protocol  
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